EP1727208A1 - Integrierter Schaltkreis und Verfahren zur Herstellung eines integrierten Schaltkreises - Google Patents

Integrierter Schaltkreis und Verfahren zur Herstellung eines integrierten Schaltkreises Download PDF

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Publication number
EP1727208A1
EP1727208A1 EP06009195A EP06009195A EP1727208A1 EP 1727208 A1 EP1727208 A1 EP 1727208A1 EP 06009195 A EP06009195 A EP 06009195A EP 06009195 A EP06009195 A EP 06009195A EP 1727208 A1 EP1727208 A1 EP 1727208A1
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EP
European Patent Office
Prior art keywords
emitter
region
resistance
semiconductor region
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP06009195A
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German (de)
English (en)
French (fr)
Inventor
Johann Dr. Dipl.-Ing. Tolonics
Klaus Dr. Locke
Peter Dipl.-Ing. Brandl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Germany GmbH
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Atmel Germany GmbH
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Publication date
Application filed by Atmel Germany GmbH filed Critical Atmel Germany GmbH
Publication of EP1727208A1 publication Critical patent/EP1727208A1/de
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7302—Bipolar junction transistors structurally associated with other devices
    • H01L29/7304—Bipolar junction transistors structurally associated with other devices the device being a resistive element, e.g. ballasting resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to an integrated circuit and a method of manufacturing an integrated circuit.
  • the emitter of a bipolar transistor with a resistor in order to achieve current negative feedback.
  • the emitter of the bipolar transistor for example, a silicide layer, which are connected for example via metal tracks of a wiring level conductively connected to the resistor.
  • bipolar transistor From the US 6,177,717 B1 Such a bipolar transistor is known.
  • an intrinsic collector of a vertical bipolar transistor is epitaxially grown on an extrinsic collector layer buried in the semiconductor substrate.
  • a lateral insulator surrounds the upper part of the intrinsic collector.
  • a silicon germanium base above the intrinsic collector and above the lateral insulator is produced by differential epitaxy.
  • An in situ doped emitter is epitaxially deposited within a window above the base such that the emitter region grows up as monocrystalline silicon in direct contact with the silicon base.
  • the invention is based on the object to further develop an integrated circuit with a bipolar transistor. This object is solved by the features of the independent claims. Advantageous developments of the invention are the subject of dependent claims.
  • an integrated circuit which has a vertically integrated bipolar transistor and at least one emitter resistor which is conductively connected to an emitter semiconductor region of the vertically integrated bipolar transistor.
  • the emitter resistor is finally defined by the conductive connection to the emitter of the bipolar transistor.
  • the emitter resistor in the integrated circuit serves as current negative feedback when the bipolar transistor is connected as an amplifier element.
  • a collector semiconductor region, a base semiconductor region and the emitter semiconductor region are arranged vertically one above another and formed monocrystalline.
  • These semiconductor regions preferably have a silicon crystal or a silicon-germanium mixed crystal doped n-conducting or p-conducting according to an npn transistor or a pnp transistor.
  • a resistance region of the emitter resistor is disposed over the emitter semiconductor region and formed monocrystalline.
  • the monocrystalline resistance region is a silicon crystal lattice with dopants that affect the conductivity of the emitter resistor.
  • the monocrystalline resistance region can also have a mixed crystal which, in addition to silicon, comprises germanium or carbon, for example.
  • the crystal lattice of the emitter resistor continues the crystal lattice of the emitter semiconductor region.
  • the resistance region has, at least in regions, a sheet resistance which is greater by at least a factor of 10 than the emitter semiconductor region.
  • the resistance region with the region with the greater sheet resistance is preferably formed at a distance from the emitter semiconductor region.
  • the resistance region with the region to a connection region of the emitter resistor is preferably formed adjacent.
  • the connection region advantageously has a silicide layer or a heavily doped layer for a low-resistance connection resistance, so that it has no significant influence on the emitter resistance value.
  • the region of the resistance region is preferably spaced from the emitter semiconductor region such that a space charge zone of the base-emitter diode advantageously does not protrude into the region of the resistance region for all operating conditions.
  • the emitter resistor has a dopant concentration profile that causes a low-resistance connection of the resistance region to the emitter semiconductor region.
  • the profile also causes a low-resistance connection to at least one further component and / or a connection of the integrated circuit.
  • a region of the emitter resistor in particular the resistance region, comprises a silicon crystal with carbon and / or germanium.
  • the carbon and the germanium can be incorporated, for example, in the silicon crystal lattice and locally change its resistance.
  • the resistance region has a dopant concentration which is less than one tenth of the dopant concentration in the emitter semiconductor region.
  • the conductance may be partially reduced, so that, for example, the vertical resistance region from the wafer surface in the direction of the wafer depth has a resistance value increasing or decreasing, for example, linearly or logarithmically.
  • the bipolar transistor and the emitter resistor are part of a high-frequency circuit, in particular a high-frequency amplifier, wherein the emitter resistor is connected as current negative feedback.
  • the invention advantageously further developing at least one further bipolar transistor is provided, which is associated with at least one further emitter resistor.
  • the sheet resistance of the further emitter resistor differs significantly from the other sheet resistor, wherein the at least two emitter resistors are processed on a wafer and the different sheet resistance is produced by masking.
  • a resistance base area of the emitter resistor preferably lies within a transistor base area of the bipolar transistor.
  • a plurality of emitter fingers of the bipolar transistor may be provided, wherein one or more emitter resistors are conductively connected to each emitter finger.
  • Another aspect of the invention is a use of a previously described integrated circuit in a high-frequency device, in particular in a radar system or in a communication system, for example in the automotive industry.
  • Another aspect of the invention is a method of manufacturing an integrated circuit.
  • a vertically integrated bipolar transistor and at least one emitter resistor is produced, wherein the emitter resistor is conductively connected to an emitter semiconductor region of the vertically integrated bipolar transistor.
  • a resistance region is monocrystalline deposited over the emitter semiconductor region by selectively depositing semiconductor material of the resistance region over the emitter semiconductor region.
  • the resistance region is epitaxially applied such that the sheet resistance of the resistance region is greater than the sheet resistance of the emitter semiconductor region.
  • the sheet resistance of the resistance region is at least a factor of 10 greater than the sheet resistance of the emitter semiconductor region.
  • a highly doped connection region can be applied between the resistance region and the emitter semiconductor region.
  • the resistance region is doped at least in regions during epitaxy in situ with a dopant concentration which is smaller by at least a factor of 10.
  • combinable process variants of the invention allow by the addition of GeH 4 gas during epitaxy that germanium atoms are introduced into the resistance region.
  • the addition of methylsilane gas during epitaxy allows carbon atoms to be introduced into the resistive region.
  • FIG. 1 shows an exemplary embodiment of a heterobipolar transistor and an emitter resistor of an integrated circuit as a sectional view through a processed wafer.
  • a portion of a monocrystalline, p-doped silicon substrate 100 is shown in which a highly doped buried layer 60 of the n-type conductivity is formed.
  • a heterobipolar transistor is produced in the following process steps. To isolate this heterobipolar transistor of further transistors or other components trench isolations are provided, which are filled with polycrystalline silicon 70 or TEOS oxide.
  • a buried silicide layer 65 of TiSi 2 is provided.
  • a monocrystalline collector semiconductor region 50 is epitaxially deposited which has a lower dopant concentration than the buried layer 60.
  • the collector semiconductor region 50 is laterally isolated from other layers and devices by a dielectric 10 of silicon dioxide.
  • the dielectric 10 also isolates a p-doped base semiconductor region 400, 410, 415.
  • the regions 400 and 410 of the base semiconductor region adjoin the collector semiconductor region 50 and are likewise monocrystalline, while the region of an external base 415 on the dielectric 10 grows polycrystalline.
  • the base semiconductor region 400, 410, 415 is applied differentially and may comprise a silicon-germanium mixed crystal to form a heterojunction.
  • a silicide layer of TiSi 2 adjoins the base semiconductor region in the region of the outer base.
  • the metallic wirings of the outer base and buried layer silicide layers 420, 65 are omitted in FIG. 1 for ease of illustration.
  • the n-doped emitter semiconductor region 300 adjoins the base semiconductor region 400 of the inner base.
  • An emitter resistor which has three regions 220, 200 and 210 adjoins the emitter semiconductor region 300 within two dielectrics 310, 320.
  • the formation of the emitter resistor takes place by epitaxially growing only monocrystalline silicon or a monocrystalline silicon-germanium layer within the emitter window formed by the dielectrics 310, 320. Outside the window no deposition occurs over silicon oxide or silicon nitride regions 10.
  • the starting point for this exemplary embodiment is therefore an opened emitter window of the npn transistor, wherein the remaining regions of at least the npn transistor are covered with an oxide or nitride layer 10.
  • the wafer is pre-cleaned with hydrofluoric acid-containing cleaning solution and subsequent drying with isopropanol of the wafer. This is followed by wafer loading, the epitaxial reactor, with a multiple nitrogen purging and evacuation cycle to reduce surface contamination.
  • a selective, in-situ doped epitaxial deposition of silicon or silicon and germanium which initially form a monocrystalline layer 220 with a high doping.
  • This layer is a connection region 220 between the resistance region 200 and the emitter semiconductor region 300.
  • a resistive region 200 of the emitter resistor is also epitaxially deposited without interruption of the epitaxial growth process so that the resistive region 200 is formed as a monocrystalline silicon-containing structure.
  • the adjustment of the emitter resistance is effected via the thickness of the epitaxial layer and / or by the concentration or the concentration profile of the doping of this resistance region 200.
  • the setting of a retrograde dopant profile is possible.
  • GeH 4 gas By adding GeH 4 gas, a defined amount of germanium can be incorporated into the silicon crystal lattice.
  • the incorporation of germanium can be used to increase the solubility and activation limit for dopants, so that the resistance of the epitaxial layer in these regions is reduced.
  • a significant increase in the dopant concentration is possible in the connection region 220 by addition of germanium.
  • this embodiment provides greater flexibility for circuit design with bipolar power transistors.
  • the resistance region 200 is connected in the embodiment of FIG. 1 by a silicide layer 210 comprising TiSi 2 for a low resistance contact resistance.
  • a silicide layer 210 comprising TiSi 2 for a low resistance contact resistance.
  • a highly doped monocrystalline or amorphous semiconductor sizing can serve for low-resistance connection.
  • This embodiment enables a chip area saving as well as a design cost reduction for the layout by integrating a vertical resistance as an emitter resistor into the emitter structure of the bipolar transistor.
  • a vertical resistance as an emitter resistor into the emitter structure of the bipolar transistor.
  • FIG. 2 schematically shows the dopant distribution along the line AA drawn in FIG.
  • the semiconductor layer 50 forms the n - doped collector with an n + highly doped subcollector 60.
  • the base solid region 400 of the inner base is p + highly doped. Adjoining the base semiconductor region 400 is the silicon semiconductor region 300 of the emitter, which is also n + -doped.
  • the emitter resistor has a connection region 220 adjacent to the emitter semiconductor region 300, which is also n + -doped. In particular there is no interface between the emitter semiconductor region 300 and the connection region 220 which could affect the charge carrier motion.
  • connection region 220 Adjoining the connection region 220 is a resistance region 200 of the emitter resistor which has a low n - doping which influences or completely determines the resistance value of the resistance region 200.
  • the emitter resistor has a connection layer 210 which, in the exemplary embodiment illustrated in FIG. 2, is a silicide layer.
  • a connection layer 210 allows the connection of the emitter resistor with another component or a connection of the integrated circuit.
  • the connection layer 210 may be highly n + doped to achieve a low connection resistance.
  • the bipolar transistor emitter resistor structure of this embodiment ensures a uniform current distribution within the emitter finger array, so that the failure rate of the integrated circuit can be reduced.
  • the adjustment of the emitter resistance is carried out via technological parameters, such as the thickness of the epitaxially grown resistance region 200, the dopant concentration profile or the concentration of foreign elements in the resistance region 200.
  • the resistance value of the resistance region 200 may be slightly influenced by the layout geometry of the resistance region 200.
EP06009195A 2005-05-10 2006-05-04 Integrierter Schaltkreis und Verfahren zur Herstellung eines integrierten Schaltkreises Withdrawn EP1727208A1 (de)

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DE102005021450A DE102005021450B4 (de) 2005-05-10 2005-05-10 Integrierter Schaltkreis und Verfahren zur Herstellung eines integrierten Schaltkreises und dessen Verwendung

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US (1) US20060255376A1 (sk)
EP (1) EP1727208A1 (sk)
DE (1) DE102005021450B4 (sk)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100117725A1 (en) * 2008-11-12 2010-05-13 Infineon Technologies Austria Ag Semiconductor diode
JP5777319B2 (ja) * 2010-10-27 2015-09-09 三菱電機株式会社 半導体装置

Citations (4)

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Publication number Priority date Publication date Assignee Title
EP0778622A2 (en) * 1995-12-08 1997-06-11 Mitsubishi Denki Kabushiki Kaisha Heterojunction bipolar transistor
US20020117684A1 (en) * 1999-08-19 2002-08-29 Hitachi, Ltd. Semiconductor device and method for fabricating the same
US6768140B1 (en) * 2002-04-03 2004-07-27 Skyworks Solutions, Inc. Structure and method in an HBT for an emitter ballast resistor with improved characteristics
DE10308870A1 (de) * 2003-02-28 2004-09-16 Austriamicrosystems Ag Bipolartransistor mit verbessertem Basis-Emitter-Übergang und Verfahren zur Herstellung

Family Cites Families (8)

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US5416354A (en) * 1989-01-06 1995-05-16 Unitrode Corporation Inverted epitaxial process semiconductor devices
EP0632505B1 (en) * 1993-07-01 1997-10-01 Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno A vertical bipolar power transistor with buried base and interdigitated geometry
EP0818829A1 (en) * 1996-07-12 1998-01-14 Hitachi, Ltd. Bipolar transistor and method of fabricating it
EP0837507B1 (en) * 1996-10-18 2004-08-18 STMicroelectronics S.r.l. A bipolar power transistor with buried base and interdigitated geometry
DE19734985B4 (de) * 1997-08-13 2010-02-11 Robert Bosch Gmbh Transistorbauelement
FR2779572B1 (fr) * 1998-06-05 2003-10-17 St Microelectronics Sa Transistor bipolaire vertical a faible bruit et procede de fabrication correspondant
US6225672B1 (en) * 1998-08-05 2001-05-01 National Science Council Of Republic Of China High-gain and high-temperature applicable phototransistor with multiple mono-crystalline silicon-carbide layers on a silicon substrate
JP4886964B2 (ja) * 2003-07-03 2012-02-29 株式会社日立製作所 半導体装置及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0778622A2 (en) * 1995-12-08 1997-06-11 Mitsubishi Denki Kabushiki Kaisha Heterojunction bipolar transistor
US20020117684A1 (en) * 1999-08-19 2002-08-29 Hitachi, Ltd. Semiconductor device and method for fabricating the same
US6768140B1 (en) * 2002-04-03 2004-07-27 Skyworks Solutions, Inc. Structure and method in an HBT for an emitter ballast resistor with improved characteristics
DE10308870A1 (de) * 2003-02-28 2004-09-16 Austriamicrosystems Ag Bipolartransistor mit verbessertem Basis-Emitter-Übergang und Verfahren zur Herstellung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HUANG C-F ET AL: "HIGH CURRENT GAIN 4H-SIC NPN BIPOLAR JUNCTION TRANSISTORS", IEEE ELECTRON DEVICE LETTERS, IEEE SERVICE CENTER, NEW YORK, NY, US, vol. 24, no. 6, June 2003 (2003-06-01), pages 396 - 398, XP001186745, ISSN: 0741-3106 *

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DE102005021450B4 (de) 2009-04-23
DE102005021450A1 (de) 2006-11-23
US20060255376A1 (en) 2006-11-16

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